Integrated chips (IC) are manufactured by subjecting a semiconductor workpiece to multiple fabrication steps. Among these, layer deposition processes are utilized to form IC components such as polysilicon gate material and metal interconnect layers within a cavity of a dielectric layer. Deposition processes include physical vapor deposition (PVD), electro-chemical plating (ECP), atomic layer deposition (ALD), etc., and require static tool calibration to maintain consistent manufacturing throughput with minimal lot-to-lot variability.